Grid-HPC WG Meeting
June 28th, 14:00-16:00 - Grid-HPC Work Group meeting Location: IGT Offices, Maskit 4, 5th Floor, Hertzliya Agenda: 14:00-14:15: OPENING - Avner & Guy 14:15-14:50: DEBUGGING AND OPTIMIZING APPLICATIONS FOR MULTICORE MPP ARCHITECTURES Speaker: Jacques Philouze, Vice President Sales & Marketing, Allinea Abstract: As two, four and potentially eight-core processors become the norm, the defacto HPC architecture is tending towards large clusters of modest 8-16 core shared-memory servers, potentially with co-processing devices (eg. GPGPUs, FPGAs, Clearspeed). Programming these machines optimally presents a number of challenges, and applications that use a mixed programming models are now becoming commonplace. In this presentation we will discuss the challenges facing today's HPC application developers, and the need for simple tools that can address mixed programming models. We will present new multicore features of Allinea's Distributed Debugging Tool (DDT) and Op...