IGT Annual Event & Exhibition

-
Dec. 3rd, 2007, The Next Generation Data Center

Click on the image for further information:

Comments

Post a Comment

Popular posts from this blog

Parallel Debugging with a Serial Debugger

-
Image
Parallel Debuggers are important tools when trying to eliminate bugs in parallel programs. Commercial parallel debuggers are expensive. In this blog post I will show you a free and open source alternative which is good enough for education purposes and for small codes. Suppose you want to debug the famous cpi.c code which computes an approximation to pi by a parallel numerical integration. This demo uses the free Data Display Debugger (ddd) which is based on gdb but has a nice GUI. Step 1, compile: mpicc -g -o cpi ./cpi.c Step 2, run (without a debugger): mpirun -np 2 ./cpi Step 3, run with the free Data Display Debugger (ddd) : mpirun -np 2 ddd ./cpi The last command will open two MPI processes (instances) of ddd each running cpi, see screen capture: Finally, I enclose here a short video which I hope is convincing: hi-res version:  https://youtu.be/N_J4NKJkuMs Happy (Free) MPI debugging!
Read more

High-Performance Linpack

-
Image
 HPL Benchmark on my laptop It's the Top500 season time. I therefore tested HPL on my laptop using Intel's latest OneAPI version 2021.1.10.2261. The laptop specifications are obtained from lscpu : $ lscpu Architecture:                    x86_64 CPU op-mode(s):                  32-bit, 64-bit Byte Order:                      Little Endian Address sizes:                   39 bits physical, 48 bits virtual CPU(s):                          8 On-line CPU(s) list:     ...
Read more

NOPs in MIPS

-
Image
The following no t e address es   questions regarding the  number of  required  NOPs in 5 stages MIPS pipelined processor.  In this example  lw  is the first instruction  follow ed  by an   add  (R-type) instruction with a RAW data dependency .     Table 1 In Table 1 we have an old MIPS which requires 3 NOPs because only after updating the architectural state (cycle 5) the add instruction can proceed.    (D)   refers to NOP instead of Decode.   Table 2 In Table 2 we assume that our  MIPS  can  write data in the first half of the clock cycle and read data in the second half  of the clock cycle  then the  number of NOPs  can be reduced  to 2.   Table 3 Finally in Table 3, like in the previous case, we assume the processor can  write data in the first half of the clock cycle and read data in the second half o...
Read more