NOPs in MIPS

The following note addresses questions regarding the number of required NOPs in 5 stages MIPS pipelined processor. In this example lw is the first instruction followed by an add (R-type) instruction with a RAW data dependency.  

Table 1









In Table 1 we have an old MIPS which requires 3 NOPs because only after updating the architectural state (cycle 5) the add instruction can proceed.  (D) refers to NOP instead of Decode. 

Table 2









In Table 2 we assume that our MIPS can write data in the first half of the clock cycle and read data in the second half of the clock cycle then the number of NOPs can be reduced to 2. 

Table 3

Finally in Table 3, like in the previous case, we assume the processor can write data in the first half of the clock cycle and read data in the second half of the clock cycle and in addition it also supports forwarding. This time the second instruction completes with just 1 NOP delay. 

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